The present invention relates generally to integrated circuit testers and methods for testing the performance of specific integrated circuits in a system level environment. More particularly, a tester arrangement that permits probing and other die level testing of an integrated circuit while it is connected and operated in a board level system is disclosed.
When debugging computer systems, a test engineer typically first attempts to determine the failing device. Once the failing device has been identified, the device is tested in order to determine exactly what is causing the fault. When integrated circuits are at fault, one common test approach is to remove the fault generating part from the system and invasively test it on an automatic tester of the type that are commercially available from a variety of vendors. Dedicated test software is then often written in order to exercise the faulty device in a manner which stimulates the failing pattern observed at a system level. Often, the writing of the test software is quite slow and time consuming. Further, in many cases it is difficult to recreate failures observed at the system level in integrated circuits that are tested independently of the system. Thus, it would be desirable to have a test system which accommodates testing faulty integrated circuits on a system level in order to permit more realistic duplication of the observed failure pattern during testing. Accordingly